Automatic test pattern generation (ATPG) is used to identify test sequences which can be applied to circuits to determine whether they operate correctly. In ATPG, test patterns are generated and used to test semiconductor devices after manufacture. Test patterns may also be used to assist in the determination of the causes of defects.
Effective testing of integrated circuits significantly enhances the ability of integrated circuit developers and manufacturers to provide reliable devices. Various techniques have been employed to test integrated circuits during the manufacturing process. One such technique that is commonly known, and has been used within the industry for over twenty years is scan testing.
Scan testing provides an efficient approach to testing the structural integrity of devices, such as flip-flops, within a complex integrated circuit. Scan testing does not test integrated circuit-level functionality. Rather, test personnel use scan testing to confirm that individual flip-flops within an integrated circuit function properly. The number of flip-flops within an integrated circuit, which is often greater than a million, presents a challenge for testing. Scan testing addresses this challenge through the use of automated test units that provide test vectors to scan paths including thousands of flip-flops within integrated circuits that have been designed to support scan testing.
Typically, complex integrated circuits are designed and implemented as a series of interconnected functional blocks, each of which can be tested independently. Devices, such as flip-flops, within these functional blocks can be designed, such that they can be connected together in a scan path to support scan testing. Flip-flops and other elements within a scan path include, in addition to inputs and outputs used for normal operation, two inputs associated with the scan testing capability. These include a scan input (SI) and a scan enable (SE) input. Flip-flops within a scan path have their output connected to the SI input of a subsequent flip-flop. The first flip-flop within a scan path receives its input from an automated test unit through a test access port on the chip. The last flip-flop within a scan path provides its output to the automated test unit through a test access port. Many scan paths can exist within a single integrated circuit.
While scan testing provides significant benefits, challenges exist related to how to efficiently debug a scan testing failure to identify the source or sources of the failure. Identifying the source of a scan path failure can be quite difficult. A typical integrated circuit can include many scan paths with each scan path including as many as 10,000 flip-flops. Additionally, when doing scan testing tens of external clock sources can exist. These external clock sources are in turn coupled through multiplexers, logic gates and buffers to form complicated clock trees, such that a single scan path can be effected by multiple clock sources with thousands of clock tree elements.
The clock pulses needed during the test mode are different than clock pulses needed during operation mode. The tests are relying on the PLL operating correctly, the OCC operating correctly, and the test logic operating correctly. At-speed transition patterns may use the OCC to generate at-speed capture pulses from the PLL. The OCC is a complex sequential MUX. When transition patterns fail during testing (e.g. at silicon), it is difficult to isolate the cause. The PLL may not be operating correctly, but observing the PLL clock at the input/output pads of the IC, after dividing the clock frequency, may not be possible. If patterns fail with at-speed capture pulses, the slow shift clock can be used for capture, and to verify the OCC operation. If the OCC is not working properly, there is currently no approach to verify this issue.